The present invention concerns a semiconductor integrated circuit device and, more in particular, it relates to a technique which is useful for applying to a semiconductor circuit integrated circuit device having a bipolar transistor.
A bipolar transistor employing a structure of EBT (Epitaxial Base Transistor) by using the technique of SPEG (Selective Poly- and Epitaxial-silicon Growth) has been reported by F. Mieno, et al (1987, IEDM, Session 2.2, PP16-19).
In the bipolar transistor employing the EBT structure, a base region is constituted with a p type semiconductor region formed to a single crystal silicon film deposited on the main surface of an n type collector region disposed in a semiconductor substrate of monocrystalline silicon. A base lead-out electrode comprising a polycrystalline silicon film introduced with a p type impurity at high concentration is electrically connected to the periphery of the base region. The base lead-out electrode is extended on an field insulation film formed on the semiconductor substrate by means of local oxidation of silicon (LOCOS) method. The base region and the base lead-out electrode are formed by using a production process inherent to the EBT structure reported as described above (SPEG technique) and they are formed in one identical production process. That is, the base region and the base lead-out electrode are formed simultaneously with a silicon film deposited on a collector region and a field insulation film by means of a CVD (Chemical Vapor Deposition) method. Among the silicon films, the silicon film deposited on the collector region is monocrystalline since the semiconductor substrate on which the collector region is formed comprises a monocrystalline silicon and this silicon film is used as the base region. On the other hand, the silicon film deposited on the field insulation film is polycrystalline since the field insulation film is amorphous and this silicon film is used as the base lead-out electrode.
An emitter region is constituted with the n type semiconductor region formed on the main surface of the base region.
In the bipolar transistor adopting the EBT structure, since the junction depth of the base region can be set with the thickness of the monocrystalline silicon film grown on the collector region, the junction depth of the base region can be made shallow. That is, since the parasitic capacitance added to the base region can be reduced, the operation speed of the bipolar transistor can be increased.